Testing of integrated circuits (IC) during fabrication is usually carried out at the end of the fabrication process. For example, a full wafer is first fabricated which includes 100's to 1000's of IC which then are diced for further testing. Wafer testing is generally carried out at the end of the fabrication because of the delicate nature of the structures placed on the wafer, firstly transistor or active elements, then a succession of conductive structures, typically metalized, for interconnect purposes and insulating structures. Normally, input/output (I/O) pads and structures are built which provide contacts for probe testing.
Probe testing necessarily requires at least one physical contact between at least one probe and corresponding I/O pads. Such contact may not be repeatable or may not be reliably performed through the potential for damage induced by the physical contact. Thus it is desirable to be able to perform testing without the requirement for physical contact. Such testing methods are termed contactless or wireless testing.
Of particular challenge and expense is process monitoring in which are conducted analog and variable measurements of critical process parameters. To date, testing at this level has required removal of wafers from the process line and contact testing off-line. It is preferable to have in-line contactless testing.
One problem with this technique is the fact that it requires physical contact with the device being accessed. Consider the example of an integrated circuit. Integrated circuits have on-chip structures for connecting the semiconductor chip to the outside world. These structures are conductive, and usually metallic in nature. Common structures (“touchpads” or “bondpads”) include pads and solder balls. Typically, test needles are brought into contact with the circuit at these touchpads in order to make a DC-coupled, wireline link by which to test the integrated circuit. Typical characteristics of the test needles include a spring force and a tip shape that induces a pressure at the point of contact.
Touchpads commonly used in modern integrated circuits to couple electronic signals are very fragile and subject to damage during mechanical probe. Damage of the touchpad can cause failure of the integrated circuit. Further, the mechanical stresses associated with mechanical contact to the structure often induces stresses into the integrated circuit beyond the conductive structure itself leading to additional failure modes of the integrated circuit. This creates other problems as well, since these structures are used later when the integrated circuit is packaged. The damage caused to the touchpads makes it difficult to connect the integrated circuit to a package or substrate, where it can interface with other electrical systems.
Another area where this physical damage causes problems is in System-in-Package (“SiP”) integration. It is known that manufacturers prefer that no pad on a SiP be probed more than one time. Such a restriction makes it difficult to touch multiple times during the assembly process flow. Thus, the testing of assembled SiP devices and the components of SiP's is a serious obstacle to large scale adoption of the technology. SiP has seen widespread adoption in memory devices using the stacked approach but little acceptance in other areas. Wireless handsets are beginning to ramp SiP manufacturing but manufacturing yields are a major concern due to Known Good Die (KGD) test reliability. The testing of such heterogeneous SiP modules is a significant and growing problem in the electronics manufacturing industry, where current test technology only allows testing after complete assembly and packaging of the SiP. Rapid growth in the highly cost conscious consumer and communications (primarily cellular phone) applications has magnified this problem. SiPs are seen as an economic way to reduce the time-to-market by the use of small specific function ICs on miniature substrates rather than the time, cost and effort to build completely integrated ICs known as System-on-Chip (SoC). Rather than the vastly more expensive complete circuit integration of SoC solutions, SiP technology enables the best-of-class, best-cost, or best-mixed technologies in separate ICs to be assembled on one SiP substrate.
Typically, the package for an integrated circuit only contains one semiconductor chip. For reasons of size, cost and performance, it is often desirable to place multiple chips inside a single package. However, if multiple, untested circuits are placed within a single package, and a single chip is defective, it becomes extremely costly or it may not be viable to replace or fix the single faulty chip. Hence the entire package, including the working dice, is discarded. This leads to inflated costs.
Consequently, it is desirable to fully test integrated circuits before they are integrated within a single package. However, when there is damage caused by the physical contact experienced in conventional test methods, it becomes difficult to integrate these chips using a SiP approach. Further, Automatic Test Equipment (ATE) and wafer probe environments involve very costly equipment and impart a significant cost to test at the wafer level. Thus semiconductor manufacturers have a dilemma balancing test cost with device yield and therefore, a new technique must be developed that does not damage the substrate during testing.
Unfortunately, testing a SiP is not the same as testing an IC. SiP testing has the challenges similar to system or PCB level testing combined with the technical challenges of chip testing. An example of the latter is the fine placement of test probes required for SiP testing. The inherent flexibility of SiP level integration means that specific ICs included on a SiP are changeable with a smaller non-recurring engineering (NRE) investment than that of a monolithic solution. This means that SiP testing methods must be flexible as well. The design-for-test of single monolithic ICs is not available in SiPs as SiPs typically don't use fully custom ICs.
Like PCB testing IC testing has evolved to include boundary scan testing which is included on many chips and built to a standard, such as the JTAG standard for testing IEEE 1149.1. Boundary scan TAP techniques allow for the testing of ICs on PCBs without the need to individually probe IC pins. This technique overcomes two major economic and technical challenges of SiP manufacturing that is, testing coverage and throughput. This method is also economic in that it uses standard automatic test equipment (ATE) infrastructure and techniques. Extensions to standard boundary scan techniques are needed for multi-device testing on SiP packages.
It is beneficial to interrogate electronic components without causing damage to the devices. One method of avoiding this physically-induced damage is to avoid physical contact altogether using a method of interrogating electronic components in a wireless (rather than wireline) manner. A method to accomplish wireless testing has been described previously. Wireless, non-contact testing can potentially alleviate many of the above SiP testing constraints, allowing for significant improvements in both the economics of SiP manufacturing, and the ability to integrate more test functions with less I/O.
There are several proven and proposed apparatus and methods for enabling contactless testing of IC, of which the following represent some of the current art:                Moore et al. in U.S. Pat. No. 6,759,863 show how a wireless test structure (ring oscillator) may be placed on wafers to gain insight into the fabrication process.        Moore et al. in U.S. Pat. No. 7,183,788 and United States Application 20070162801 describes aspects of control mechanisms on wafers.        Slupsky et al. in U.S. Pat. Nos. 6,885,202 and 7,109,730 describe micro fabrication and I/O cells for IC on-wafers.        Kwark in U.S. Pat. No. 7,215,133 describe die level device differencing with single ended output.        Khandros et al. in U.S. Pat. Nos. 7,202,687 and 7,218,094 Khandros describe forms of signal transfer to testers.        Aghababazadeh et al. in U.S. Pat. No. 7,256,055 describe use of thermal junctions to power test structures.        Walker et al. in U.S. Pat. No. 6,374,379 describe a low cost configuration for monitoring and controlling parametric measurement units in automatic test equipment. The patent discusses block diagram implementation of a PMU.        Ralston-Good et al. in United States Patent Application 2007239163-001 describes die level test structures on wafer.        Roberts, et al. in U.S. Pat. No. 7,242,209 disclose a design for test elements for inclusion in IC.        Hess et al. in 2007 IEEE International Conference on Microelectronic Test Structures, March 19-22, Tokyo, Japan. Paper 7.4; describe an array structure for testing various transistors in a wafer scribe line using contact probes.        Sayil et al. in “Comparison of contactless measurement and testing techniques to a new All-Silicon optical test and characterization method,” IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 5, pp. 2082-2089, October 2005, present a comparison of eight non-contact probing methods. The optical testing of CMOS dies is of particular focus.        
The present method for wireless communication is that of inductive coupling. A current flowing through one inductor generates a magnetic field which extends beyond the inductor. This field induces current in another inductor within close proximity of the first inductor, coupling the two inductors together.
RF techniques are then used to transmit data between the inductors. For example, a digital signal can be modulated by a carrier wave, and then driven through an inductor. The receiving inductor picks up some fraction of this modulated wave, and passes the signal on to a receiver circuit. The use of RF techniques for transmitting data is the reason the inductors are sometimes called “antennae.” Many microfabricated antenna designs have been, and continue to be, researched for various applications such as clocking and data transfer. These designs are generally intended for non-test applications and do not meet the cost, performance and data integrity requirements for applications such as SiP testing. The designs presented here create RF transceivers meeting the cost and performance goals of SiP applications. Specialized RF CMOS technologies and other technologies like SiGe are not used for the stated economic reasons, but the concepts may be implemented in these processes for technical reasons. Although many designs may be used for transmitting and receiving data wirelessly, many are not suitable in wafer testing applications since they require a large power budget, or utilize large amounts of silicon real estate on the device under test (DUT) or probe. Additionally, the bit error rate for testing purposes must be extremely low.
The use of RF based interconnects alleviates the need to reduce the number of touch downs on signal i/o (input/output) pads. Further, as has been discussed, KGD levels improve dramatically since a more thorough wafer level test is performed. These two benefits combine to suggest RF based interconnects provide a means for improving SiP process test flow and consequently manufacturing yields.
The method of wireless communication is not limited to inductive coupling, however. It is possible to use other forms of near-field communication, such as capacitive coupling, for communication. As well, far-field communication is also a viable technique, where one antenna receives far-field radiation from a transmitting antenna. Further, optical methods such as lasers, photo diodes, and electro-optic components may be used to couple electronic circuits. Another method involves the use of magnetics such as high speed magnetic circuit (MR, GMR, TMR, etc.) components to couple electronic circuits.
One method for improving manufacturing yields is to perform tests of the SiP during the manufacturing process flow. Such testing enables defects to be identified early in the process and rework and repair to be affected or the component can be discarded and reduces the cost of the discard by eliminating additional process steps and their associated additional value. The implementation of a process flow with just one repair step can have a significant impact on manufacturing yield. SiP's are manufactured with materials that are susceptible to probe damage in the same way as CMOS VLSI integrated circuits.
However, wireless access has limitations. One limitation is that there may be a need to provide power to the device being accessed. A limited amount of power can be provided without physical contact to a chip undergoing access, for example, but the amount of power may be inadequate for accessing of complex multi-component circuits on such a chip. Hence it would be more beneficial to develop a method for accessing electronic components in which the probe can be configured to interface one or both of wireless access and a wireline access methods.
One method to allow physical probing without causing damage is to “ruggedize” the physical contact. For example, use thick metal that will withstand multiple touchdowns or metallurgy that is not compatible with standard manufacturing techniques for integrated circuits but may be applied in a post process. Such metallurgy may include gold contacts, tungsten contacts, etc.
System-in-Package Testing
The testing of SiP modules is a significant and growing problem in the electronics manufacturing industry. In only eight years SiP packaging has grown from less than 5% to nearly 50% of the packaged IC market. Thus SiPs and SiP testing have become multi-billion dollar industries in a very short time. The Semiconductor Industry Association (SIA) defines a SiP as any combination of semiconductors, passives, and interconnects integrated into a single package. SiP economics are based on the ability to combine multiple different technologies (active and passive) into a miniature package.
SiPs are analogous to PCBs (printer circuit board) in the sense that multiple chips and passives are combined using one substrate. SiPs use passive substrates and various technologies combined in a miniature package, including Si, SiGe, 0.13 um, 0.25 um, digital, analogue, RF, bare die, flip chip ICs, etc. However, unlike PCBs the miniature size of SiPs precludes normal testing as the signal connections and the IC pads themselves are miniature and inaccessible, or occupied. Based on experience during development of the IC industry, the cost of testing a SiP is anticipated to grow more quickly than its manufacturing cost as SiPs evolve into more complex designs.
A SiP has the functional complexity comparable to a populated PCB, combined with the inability to provide access or test points for internal signals. Classical PCB testing has evolved to improve test time and coverage by providing the concept of a Test Access Port (TAP), which gives access to signals on the PCB. The test access port, for which the most common standard is JTAG IEEE 1149.1, is used to assist in fault location and thus enable PCB repair and retest in an efficient manner. Repair and retest of SiPs is not viable given their assembly and construction methods. Testing a SiP is not the same as testing an IC. SiP testing has the challenges similar to system or PCB level testing combined with the technical challenges of chip testing. An example of the latter is the fine placement of test probes required for SiP testing. The inherent flexibility of SiP level integration means that specific ICs included on a SiP are changeable with a smaller non-recurring engineering (NRE) investment than that of a monolithic solution. This means that SiP testing methods must be flexible as well. The design-for-test of single monolithic ICs is not available in SiPs as SiPs typically do not use fully customized ICs. Like PCB testing, IC testing has evolved to include boundary scan testing which is included on many chips and built into the JTAG standard for testing. IEEE 1149.1. JTAG TAP techniques allow for the testing of ICs on PCBs without the need to individually probe IC pins.
Package Testing
The earlier mentioned PCB and IC test issues continue for SiP packaging where a set of VLSI ICs, and discrete components are placed onto substrates to create a compact system. SiP assembly includes bare die and flip chip techniques to provide very high levels of system integration in a physically small but low cost package. Additionally, passives can be included as separate parts or even integrated in the SiP substrate. The substrates used in SiPs are evolving along the same path as that of ICs with finer features and greater complexity. The ability to produce large numbers of SiPs simultaneously on a single wafer produces a bottleneck as SiP testing is currently done serially.
The addition of each IC to a SiP substrate has a negative impact on yield during production. Typically, the final packaging is done without the ability to test devices as they are added to the SiP substrate. Even when there is the ability to test devices as they are added to SiPs it is currently not done because of yield loss due to the potential for damage resulting from multiple test probe touchdowns. SiP probe testing requires touchdown and scrubbing of IC Pads. Scrubbing creates some damage on pads, which affects their ability to be wirebonded to the SiP. Another cost is that there is a need for multiple probe card designs for each manufacturing step or individual SiP design. A further reason pre-package testing is limited in manufacture of SiPs is that the number of signals/pads is large if they are individually tested. Additionally, if IC pads on SiPs were accessible for massively parallel contact probe testing there would be yield loss in subsequent wirebonding-manufacturing steps. Even without these issues it is difficult to conceive of how intermediate tests can be done using physical contact methods because of the three-dimensional nature of the SiP assemblies and mixed technologies (flip chip, wire bond, surface mount, discrete etc.) used in manufacturing SiPs. While technology is available to enable such testing, the costs would be very high, requiring investment in multiple multi-level custom probe cards, test stations and time which would be detrimental to SiP economics.
The growth in SiP design wins is driven by cost and the ability to produce miniature yet advanced products. Using Known Good Dies (KGD) is a way to increase yield in products. However, for SiPs it is not always possible or feasible for cost and test time reasons. Thus, for economic reasons, electronics manufacturers often use untested SiPs, partially tested or only wafer tested dies. This means that there is an enhanced level of rejected components, and resultant waste, built into the SiP manufacturing process as it is currently practiced. Because SiPs are normally tested only after packaging, a test coverage gap is created between the starting dies and the final packaged SiP. This gap or test blindness zone can cause problems especially on large volume products, which is the main target of SiP technology. Thus yield improvement is very difficult, and the invested assembly and packaging cost is invested on all units, including nonfunctional ones. Without mid stream testing there is no opportunity to cull defective devices early in the manufacturing value chain. The complete packaging investment is wasted on non-functional SiPs, whose condition is only visible at the end of the packaging process. Yield loss when mounting dies or passives remains invisible without the ability to do test during production. With half of all packaged systems being SiPs, and SiPs only being tested after assembly, there are severe economic costs arising from test blindness.
Thus there is a need for a fast, flexible, and nondestructive method and apparatus for testing of electronic components, such as SiPs.